Digital Hardware Engineer (FE)

Role Description

This is a full-time on-site role for a Digital Design Engineer at Mosaic SoC in Zurich. The Digital Design Engineer will be responsible for tasks related to digital circuit design, RTL coding, simulation and verification.

Key Responsibilities

  • Design and implement digital hardware using Verilog/SystemVerilog, with a focus on RISC-V-based architectures.
  • Develop and optimize RTL code for energy-efficient, low-power designs.
  • Collaborate with the architecture team to define and implement microarchitecture specifications for RISC-V-based systems.
  • Utilize EDA tools for simulation, synthesis and other design tasks.
  • Perform functional verification of RTL designs, including writing testbenches and debugging simulation results.
  • Integrate hardware components into complete systems, ensuring compatibility with embedded software.
  • Develop, test, and debug embedded software in C and assembly to support hardware functionality.
  • Conduct performance analysis and optimization of digital designs.
  • Document design processes, test results, and implementation details for cross-functional collaboration.

Required Qualifications

  • Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • Proven experience in digital hardware design with Verilog/SystemVerilog.
  • Familiarity with RISC-V ISA and microarchitecture design principles.
  • Familiarity with modern SoC design flows, including IP integration and verification.
  • Hands-on experience with EDA tools (e.g., Synopsys, Cadence, Open Source) for simulation and synthesis
  • Strong understanding of computer architecture, memory hierarchies, and processor pipelines.
  • Familiarity with scripting languages (e.g., Python, Perl, TCL) for automation tasks.

Ideal Experience

  • Experience with FPGA implementation and hardware/software co-design.
  • Proficiency in embedded software development using C and assembly languages.

Digital Hardware Engineer (BE)

Role DescriptionThis is a full-time on-site role for a Digital Design Engineer at Mosaic SoC in Zurich. The role emphasizes back-end digital design, including RTL-to-GDSII implementation, physical design, and timing closure, alongside RTL development and verification.

Key Responsibilities

  • Implement and optimize digital designs through the full back-end flow (synthesis, place & route, CTS, STA, signoff).
  • Harden RTL in Verilog/SystemVerilog for physical implementation.
  • Define and manage synthesis design constraints (SDC), including clocking, timing exceptions.
  • Define and manage physical design constraints and implementation flows, e.g. multi-mode/multi-corner scenarios.
  • Perform static timing analysis (STA) and power analysis.
  • Debug and resolve issues across the design flow, from RTL to post-layout.
  • Contribute to automation and flow improvements using automated test flows.
  • Document implementation results, constraints, and signoff reports.

Required Qualifications

  • Master’s degree in Electrical Engineering, Computer Engineering.
  • Strong experience in back-end digital design (synthesis, P&R, STA, timing closure).
  • Solid understanding of physical design concepts: floorplanning, clock tree synthesis, routing, and signoff.
  • Good working knowledge of Verilog/SystemVerilog with awareness of synthesis and physical implications.
  • Experience with industry-standard EDA tools (e.g., Synopsys, Cadence, Siemens).
  • Strong knowledge of timing analysis, constraints, and low-power design techniques.
  • Familiarity with SoC integration and modern chip design flows.
  • Experience with scripting (Python, Tcl) for automation and flow development.

Ideal Experience

  • Experience with sub-10nm technology nodes
  • Experience with UPF design flows for low power architectures
  • Experience with advance packaging, e.g. BGA
  • Prior experience in leading tapeouts from synthesis to signoff

Compiler Engineer

Role Description

This is a full-time on-site role for a Compiler Engineer at Mosaic SoC in Zurich. The Compiler Engineer will focus on developing, optimizing, and maintaining compiler toolchains for cutting-edge RISC-V-based systems, ensuring efficient code generation and tight integration with energy-efficient hardware architectures.

Key Responsibilities

  • Design, implement, and optimize compilers targeting highly customized heterogeneous RISC-V architectures.
  • Analyze and improve generated code with respect to execution speed and memory usage.
  • Collaborate closely with hardware and architecture teams to co-design ISA features, accelerator integration, and compiler support.
  • Perform low-level performance analysis and benchmarking across simulation and real hardware platforms.
  • Develop and maintain continuous integration and deployment workflows to automate testing, benchmarking, and cross-platform building of toolchains.
  • Document compiler architecture, optimization strategies, and toolchain usage for internal teams and customers.

Required Qualifications

  • Master’s degree or Doctorate in Computer Science, Electrical Engineering or related fields. Equivalent work experience is acceptable.
  • Prior experience in compiler development, preferably MLIR but also LLVM, GCC or other toolchains.
  • Strong proficiency in C/C++ and familiarity with low-level programming (assembly).
  • Solid understanding of compiler internals, including IR design, optimization passes, and code generation.
  • Experience with performance analysis, debugging, and optimization at the compiler and system level.

Ideal Experience

  • Familiarity with RISC-V ISA including custom extensions is a plus.
  • Hands-on experience with simulation, FPGA prototypes, or prototype hardware platforms for validating compiled code.
  • Strong understanding of computer architecture, including pipelines, memory hierarchies, and instruction-level performance.
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